EPM3064ATC-100-10N vs EPM3064ATC100-7 Comparison

Detailed side-by-side comparison of EPM3064ATC-100-10N by Altera and EPM3064ATC100-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC-100-10N

EPM3064ATC-100-10N - 64-Macrocell MAX 3000A CPLD, 10ns | Altera

EPM3064ATC-100-10N βœ“ Active
Altera
EPM3064ATC100-7

EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera

EPM3064ATC100-7 Obsolete

Specification Comparison

Parameter EPM3064ATC-100-10N EPM3064ATC100-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $2.20 $3.08
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macro Cells 64 β€”
Logic Array Blocks (LABs) 2 2
User I/O Pins 66 β€”
Usable Gates (min) 600 β€”
Usable Gates (typical) 1,250 β€”
Pin-to-Pin Delay (tPD) 10 ns β€”
Counter Frequency (fCNT) 227.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
In-System Programmability Yes (IEEE 1532 / JTAG 1149.1) β€”
Programming Interface 4-pin JTAG (TCK/TMS/TDI/TDO) β€”
Package TQFP-100 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
RoHS Status Compliant β€”
Usable Gates β€” 1,250
Macrocells β€” 64
Maximum User I/Os β€” 66 (in 100-pin TQFP)
Pin-to-Pin Propagation Delay (tPD) β€” 7.5 ns (-7 speed grade)
Maximum Internal Counter Frequency β€” 135.1 MHz
Supply Voltage - VCCINT (Core) β€” 3.3 V
Supply Voltage - VCCIO (I/O) β€” 2.5 V or 3.3 V (5.0 V tolerant inputs)
Technology β€” CMOS EEPROM
In-System Programming (ISP) β€” Yes, via IEEE 1149.1 JTAG
PCI Compliance β€” PCI Local Bus Specification Revision 2.2
JTAG Boundary Scan β€” Yes
Lead Free / RoHS β€” Compliant (modern shipments)

Datasheets & Resources

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