EPM3064ATC-100-10N vs EPM3064ATC100-7 比較
詳細な並列比較: EPM3064ATC-100-10N メーカー: Altera および EPM3064ATC100-7 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 Obsolete仕様比較
| パラメータ | EPM3064ATC-100-10N | EPM3064ATC100-7 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $2.20 | $3.08 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 66 | — |
| Usable Gates (min) | 600 | — |
| Usable Gates (typical) | 1,250 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| In-System Programmability | Yes (IEEE 1532 / JTAG 1149.1) | — |
| Programming Interface | 4-pin JTAG (TCK/TMS/TDI/TDO) | — |
| パッケージ | TQFP-100 | 100-pin TQFP |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS ステータス | Compliant | — |
| Usable Gates | — | 1,250 |
| Macrocells | — | 64 |
| Maximum User I/Os | — | 66 (in 100-pin TQFP) |
| Pin-to-Pin Propagation Delay (tPD) | — | 7.5 ns (-7 speed grade) |
| Maximum Internal Counter Frequency | — | 135.1 MHz |
| Supply Voltage - VCCINT (Core) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Technology | — | CMOS EEPROM |
| In-System Programming (ISP) | — | Yes, via IEEE 1149.1 JTAG |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 |
| JTAG Boundary Scan | — | Yes |
| Lead Free / RoHS | — | Compliant (modern shipments) |