EPM3064ATC100-10NA vs EPM3064AT100-10N Comparison
Detailed side-by-side comparison of EPM3064ATC100-10NA by Intel and EPM3064AT100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3064ATC100-10NA - MAX 3000A CPLD, 64 Macrocells, 10ns, TQFP-100 | Intel (Altera)
EPM3064ATC100-10NA β ActiveSpecification Comparison
| Parameter | EPM3064ATC100-10NA | EPM3064AT100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.65 | $5.45 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| User I/Os | 66 | β |
| Usable Gates | 1,250 | 1,250 |
| Logic Array Blocks (LABs) | 4 | 4 |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX in MHz] | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| MultiVolt I/O Voltages | 2.5 V / 3.3 V / 5.0 V | β |
| Package | TQFP-100 (0.5 mm pitch) | TQFP-100 (T100), 14 mm x 14 mm |
| Configuration Memory | Non-volatile EEPROM | EEPROM (non-volatile) |
| In-System Programming | IEEE Std. 1532 compliant | β |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Lead-Free / RoHS | Yes (NA suffix) | β |
| User I/O Pins | β | 66 |
| Speed Grade | β | -10 (10 ns pin-to-pin delay) |
| I/O Bank Voltage | β | 3.3 V |
| 5 V Tolerant Inputs | β | Yes (via clamping diodes) |
| Programming Interface | β | JTAG (IEEE Std. 1149.1) with pin-locking |
| ISP Compliance | β | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | IEEE Std. 1149.1 compliant |
| Operating Temperature (Commercial) | β | 0C to +70C |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | β | [DATA_NEEDED: lead-free finish] |