EPM3064ATC100-7 vs EPM3064ATC100-4N Comparison
Detailed side-by-side comparison of EPM3064ATC100-7 by Altera and EPM3064ATC100-4N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 ObsoleteSpecification Comparison
| Parameter | EPM3064ATC100-7 | EPM3064ATC100-4N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.08 | $4.60 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 1,250 | 1,250 |
| Macrocells | 64 | β |
| Logic Array Blocks (LABs) | 2 | β |
| Maximum User I/Os | 66 (in 100-pin TQFP) | β |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | β |
| Maximum Internal Counter Frequency | 135.1 MHz | β |
| Supply Voltage - VCCINT (Core) | 3.3 V | β |
| Supply Voltage - VCCIO (I/O) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | β |
| Technology | CMOS EEPROM | β |
| Package | 100-pin TQFP | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| In-System Programming (ISP) | Yes, via IEEE 1149.1 JTAG | β |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | β |
| JTAG Boundary Scan | Yes | β |
| Lead Free / RoHS | Compliant (modern shipments) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 64 |
| Logic Array Blocks | β | 2 |
| User I/O Pins | β | 66 |
| Pin-to-Pin Delay (tPD) | β | 4.5 ns |
| Counter Frequency | β | 222.2 MHz (max) |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V |
| Programming Interface | β | IEEE Std. 1149.1 JTAG (ISP) |
| ISP Standard | β | IEEE Std. 1532 |
| Process Technology | β | CMOS EEPROM |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |