EPM3064ATC100-7 vs EPM3064ATC100-4N 比較
詳細並排比較 EPM3064ATC100-7 由 Altera 與 EPM3064ATC100-4N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3064ATC100-7 - MAX 3000A 64-Macrocell CPLD, 7.5ns, 100-TQFP | Altera
EPM3064ATC100-7 Obsolete規格比較
| 參數 | EPM3064ATC100-7 | EPM3064ATC100-4N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 1,250 | 1,250 |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | — |
| Maximum User I/Os | 66 (in 100-pin TQFP) | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Maximum Internal Counter Frequency | 135.1 MHz | — |
| Supply Voltage - VCCINT (Core) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Technology | CMOS EEPROM | — |
| 封裝 | 100-pin TQFP | 100-pin TQFP |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| In-System Programming (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| JTAG Boundary Scan | Yes | — |
| Lead Free / RoHS | Compliant (modern shipments) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Counter Frequency | — | 222.2 MHz (max) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |
| ISP Standard | — | IEEE Std. 1532 |
| Process Technology | — | CMOS EEPROM |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |