EPM3064ATC44-4N vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ATC44-4N by Altera and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATC44-4N EPM3064ATC44-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $3.45 $2.30
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 64
Logic Array Blocks 2 2
Number of I/Os 34 β€”
Dedicated Inputs 4 β€”
Usable Gates 1,250 1,250
Propagation Delay (tpd) 4.5 ns β€”
Maximum Counter Frequency 222.2 MHz 192.3 MHz (-7 grade)
Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V β€”
Programmability EEPROM, in-system programmable (JTAG) EEPROM, in-system programmable (ISP)
JTAG Support IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) β€”
Operating Temperature 0C to +70C (commercial) 0Β°C to +85Β°C (commercial)
Package 44-pin TQFP 44-pin TQFP
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: rohs status] Compliant
User I/O Pins β€” 34
Number of Pins β€” 44
Speed Grade β€” -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Supply Voltage (VCC) β€” 3.3 V
MultiVolt I/O β€” 1.8 V / 2.5 V / 3.3 V
JTAG Interface β€” IEEE Std. 1149.1 compliant
ISP Standard β€” IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Built-in, JTAG-driven

Datasheets & Resources

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