EPM3064ATC44-7N vs EPM3064ATC44-10NAF Comparison
Detailed side-by-side comparison of EPM3064ATC44-7N by Altera and EPM3064ATC44-10NAF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndSpecification Comparison
| Parameter | EPM3064ATC44-7N | EPM3064ATC44-10NAF |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $2.30 | $5.05 |
| Family | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | β |
| Usable Gates | 1,250 | 1250 |
| User I/O Pins | 34 | β |
| Number of Pins | 44 | β |
| Speed Grade | -7 (7.5 ns pin-to-pin delay) | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Maximum Counter Frequency | 192.3 MHz (-7 grade) | β |
| Supply Voltage (VCC) | 3.3 V | β |
| MultiVolt I/O | 1.8 V / 2.5 V / 3.3 V | β |
| Programmability | EEPROM, in-system programmable (ISP) | β |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| ISP Standard | IEEE Std. 1532 compliant | β |
| Boundary-Scan Test (BST) | Built-in, JTAG-driven | β |
| Package | 44-pin TQFP | TQFP-44 (10x10 mm) |
| Operating Temperature | 0Β°C to +85Β°C (commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant | Compliant |
| Series | β | MAX 3000A |
| Logic Elements / LABs | β | 4 LABs (16 macrocells per LAB) |
| Number of I/O Pins | β | 34 |
| Propagation Delay (tPD, max) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V |
| I/O Voltage Tolerance | β | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) |
| Programmable Technology | β | EEPROM (non-volatile) |
| In-System Programmable | β | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | β | Yes (IEEE Std. 1149.1 JTAG) |
| Pin-Locking | β | Yes |
| Lead Finish | β | Lead-free (NiPdAu, AF suffix) |
| Configuration Memory Cycles | β | 100 erase/program cycles |