EPM3064ATC44-7N vs EPM3064ATC44-10NAF 比較
詳細並排比較 EPM3064ATC44-7N 由 Altera 與 EPM3064ATC44-10NAF 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF Nrnd規格比較
| 參數 | EPM3064ATC44-7N | EPM3064ATC44-10NAF |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | 1250 |
| User I/O Pins | 34 | — |
| 腳位數 | 44 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 192.3 MHz (-7 grade) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| MultiVolt I/O | 1.8 V / 2.5 V / 3.3 V | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| ISP Standard | IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Built-in, JTAG-driven | — |
| 封裝 | 44-pin TQFP | TQFP-44 (10x10 mm) |
| 工作溫度 | 0°C to +85°C (commercial) | [DATA_NEEDED: industrial/commercial grade] |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | Compliant | Compliant |
| Series | — | MAX 3000A |
| Logic Elements / LABs | — | 4 LABs (16 macrocells per LAB) |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD, max) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage Tolerance | — | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) |
| Programmable Technology | — | EEPROM (non-volatile) |
| In-System Programmable | — | Yes (IEEE Std. 1532 compliant) |
| Boundary-Scan Test | — | Yes (IEEE Std. 1149.1 JTAG) |
| Pin-Locking | — | Yes |
| Lead Finish | — | Lead-free (NiPdAu, AF suffix) |
| Configuration Memory Cycles | — | 100 erase/program cycles |