EPM3064ATI44-10 vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ATI44-10 by Intel and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-10 EPM3064ATC44-7N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type In-System Programmable (ISP), EEPROM-based —
Number of Macrocells 64 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,250 —
Number of User I/O Pins 34 —
Package TQFP-44 (10x10 mm, 0.8 mm pitch) 44-pin TQFP
Pin-to-Pin Delay (tPD) 10 ns 7.5 ns
Maximum Counter Frequency 227.3 MHz 192.3 MHz (-7 grade)
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage Tolerance 5.0 V tolerant (MultiVolt I/O) —
JTAG Interface IEEE Std. 1149.1 compliant IEEE Std. 1149.1 compliant
ISP Standard IEEE Std. 1532 IEEE Std. 1532 compliant
Operating Temperature -40C to +85C (Industrial) 0°C to +85°C (commercial)
RoHS Status Non-Compliant (contains lead, per DigiChip listing) Compliant
Lead Free Status Contains Lead —
Mounting Type Surface Mount Surface Mount
Process Technology CMOS, EEPROM —
Programming Cycles [DATA_NEEDED: typical program/erase endurance] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Array Blocks — 2
Usable Gates — 1,250
User I/O Pins — 34
Number of Pins — 44
Speed Grade — -7 (7.5 ns pin-to-pin delay)
Supply Voltage (VCC) — 3.3 V
MultiVolt I/O — 1.8 V / 2.5 V / 3.3 V
Programmability — EEPROM, in-system programmable (ISP)
Boundary-Scan Test (BST) — Built-in, JTAG-driven

Datasheets & Resources

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