EPM3064ATI44-10 vs EPM3064ATC44-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-10 sa pamamagitan ng Intel at EPM3064ATC44-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATI44-10 | EPM3064ATC44-7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | — |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,250 | — |
| Number of User I/O Pins | 34 | — |
| Packhaging | TQFP-44 (10x10 mm, 0.8 mm pitch) | 44-pin TQFP |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns |
| Maximum Counter Frequency | 227.3 MHz | 192.3 MHz (-7 grade) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant (MultiVolt I/O) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | IEEE Std. 1149.1 compliant |
| ISP Standard | IEEE Std. 1532 | IEEE Std. 1532 compliant |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0°C to +85°C (commercial) |
| Tindminan RoHS | Non-Compliant (contains lead, per DigiChip listing) | Compliant |
| Lead Free Status | Contains Lead | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM | — |
| Programming Cycles | [DATA_NEEDED: typical program/erase endurance] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Array Blocks | — | 2 |
| Usable Gates | — | 1,250 |
| User I/O Pins | — | 34 |
| Bilang ng Pins | — | 44 |
| Speed Grade | — | -7 (7.5 ns pin-to-pin delay) |
| Supply Voltage (VCC) | — | 3.3 V |
| MultiVolt I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Test (BST) | — | Built-in, JTAG-driven |