EPM3064ATI44-10 vs EPM3064ATI44-10N Comparison
Detailed side-by-side comparison of EPM3064ATI44-10 by Intel and EPM3064ATI44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3064ATI44-10
EPM3064ATI44-10 - 64-Macrocell MAX 3000A CPLD, TQFP-44 | Intel / Altera
EPM3064ATI44-10 NrndAltera
EPM3064ATI44-10N
EPM3064ATI44-10N - 64-Macrocell 3.3V ISP CPLD | Intel / Altera
EPM3064ATI44-10N ObsoleteSpecification Comparison
| Parameter | EPM3064ATI44-10 | EPM3064ATI44-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.65 | $3.95 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | In-System Programmable (EEPROM) |
| Number of Macrocells | 64 | β |
| Number of Logic Array Blocks (LABs) | 4 | β |
| Number of Usable Gates | 1,250 | β |
| Number of User I/O Pins | 34 | β |
| Package | TQFP-44 (10x10 mm, 0.8 mm pitch) | 44-pin TQFP |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency | 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Voltage Tolerance | 5.0 V tolerant (MultiVolt I/O) | β |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| ISP Standard | IEEE Std. 1532 | β |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial, "N" suffix) |
| RoHS Status | Non-Compliant (contains lead, per DigiChip listing) | Non-Compliant (per digchip datasheet excerpt) |
| Lead Free Status | Contains Lead | β |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM | CMOS EEPROM |
| Programming Cycles | [DATA_NEEDED: typical program/erase endurance] | β |
| Macrocells | β | 64 |
| Usable Gates | β | 1250 |
| User I/Os | β | 34 |
| Dedicated Inputs | β | 4 |
| Logic Blocks | β | 4 |
| Pin-to-Pin Delay | β | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | β | 100 MHz |
| ISP Interface | β | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | β | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V (MultiVolt) |
| Boundary-Scan Test | β | Built-in (JTAG) |
| Lead-Free Status | β | Contains Lead (per digchip datasheet excerpt) |