EPM3064ATI44-10 vs EPM3064ATI44-10N 비교

다음의 상세 나란히 비교: EPM3064ATI44-10 제조: Intel 및 EPM3064ATI44-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM3064ATI44-10 EPM3064ATI44-10N
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND Obsolete
재고 상태 In Stock In Stock
단가 (USD) $7.65 $3.95
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Programmable Type In-System Programmable (ISP), EEPROM-based In-System Programmable (EEPROM)
Number of Macrocells 64 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,250 —
Number of User I/O Pins 34 —
패키지 TQFP-44 (10x10 mm, 0.8 mm pitch) 44-pin TQFP
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage Tolerance 5.0 V tolerant (MultiVolt I/O) —
JTAG Interface IEEE Std. 1149.1 compliant —
ISP Standard IEEE Std. 1532 —
동작 온도 -40C to +85C (Industrial) -40C to +85C (Industrial, "N" suffix)
RoHS 상태 Non-Compliant (contains lead, per DigiChip listing) Non-Compliant (per digchip datasheet excerpt)
Lead Free Status Contains Lead —
실장 유형 Surface Mount Surface Mount
Process Technology CMOS, EEPROM CMOS EEPROM
Programming Cycles [DATA_NEEDED: typical program/erase endurance] —
Macrocells — 64
Usable Gates — 1250
User I/Os — 34
Dedicated Inputs — 4
Logic Blocks — 4
Pin-to-Pin Delay — 10 ns (-10 speed grade)
Maximum Frequency (fMAX) — 100 MHz
ISP Interface — IEEE Std. 1149.1 (JTAG)
ISP Standard Compliance — IEEE Std. 1532
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V (MultiVolt)
Boundary-Scan Test — Built-in (JTAG)
Lead-Free Status — Contains Lead (per digchip datasheet excerpt)

데이터시트 & 자료

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