EPM3064ATI44-10 vs EPM3064ATI44-10N Comparação
Comparação detalhada lado a lado de EPM3064ATI44-10 por Intel e EPM3064ATI44-10N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Comparação de especificações
| Parâmetro | EPM3064ATI44-10 | EPM3064ATI44-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | NRND | Obsolete |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $7,65 | $3,95 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | In-System Programmable (EEPROM) |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,250 | — |
| Number of User I/O Pins | 34 | — |
| Encapsulamento | TQFP-44 (10x10 mm, 0.8 mm pitch) | 44-pin TQFP |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant (MultiVolt I/O) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| ISP Standard | IEEE Std. 1532 | — |
| Temperatura de operação | -40C to +85C (Industrial) | -40C to +85C (Industrial, "N" suffix) |
| Status RoHS | Non-Compliant (contains lead, per DigiChip listing) | Non-Compliant (per digchip datasheet excerpt) |
| Lead Free Status | Contains Lead | — |
| Tipo de montagem | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM | CMOS EEPROM |
| Programming Cycles | [DATA_NEEDED: typical program/erase endurance] | — |
| Macrocells | — | 64 |
| Usable Gates | — | 1250 |
| User I/Os | — | 34 |
| Dedicated Inputs | — | 4 |
| Logic Blocks | — | 4 |
| Pin-to-Pin Delay | — | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | — | 100 MHz |
| ISP Interface | — | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V (MultiVolt) |
| Boundary-Scan Test | — | Built-in (JTAG) |
| Lead-Free Status | — | Contains Lead (per digchip datasheet excerpt) |