EPM3064ATI44-10NAD vs EPM3064ATC44-10NAF Comparison

Detailed side-by-side comparison of EPM3064ATI44-10NAD by Altera and EPM3064ATC44-10NAF by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-10NAD EPM3064ATC44-10NAF
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $4.10 $5.05
Family MAX 3000A β€”
Macrocells 64 β€”
Usable Gates 1,250 1250
Logic Array Blocks (LABs) 4 (16 macrocells each) β€”
User I/Os (max) 34 β€”
Pin-to-Pin Delay (tPD) 10 ns β€”
Setup Time (tSU) 4.5 ns β€”
Core Voltage (VCCINT) 3.3 V β€”
I/O Voltage (VCCIO) 3.3 V or 2.5 V β€”
Package TQFP-44 TQFP-44 (10x10 mm)
Operating Temperature -40C to +85C (Industrial) [DATA_NEEDED: industrial/commercial grade]
Programming Interface JTAG (IEEE Std. 1532 compliant) β€”
In-System Programmable Yes Yes (IEEE Std. 1532 compliant)
RoHS Status Compliant Compliant
Mounting Type Surface Mount Surface Mount
Series β€” MAX 3000A
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
Logic Elements / LABs β€” 4 LABs (16 macrocells per LAB)
Number of I/O Pins β€” 34
Propagation Delay (tPD, max) β€” 10 ns
Supply Voltage (VCCINT) β€” 3.0 V to 3.6 V
I/O Voltage Tolerance β€” Multi-voltage (3.3 V / 2.5 V / 1.8 V capable)
Programmable Technology β€” EEPROM (non-volatile)
Boundary-Scan Test β€” Yes (IEEE Std. 1149.1 JTAG)
Pin-Locking β€” Yes
Lead Finish β€” Lead-free (NiPdAu, AF suffix)
Configuration Memory Cycles β€” 100 erase/program cycles

Datasheets & Resources

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