EPM3064ATI44-10NAD vs EPM3064ATC44-10NAF Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-10NAD sa pamamagitan ng Altera at EPM3064ATC44-10NAF sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATI44-10NAD EPM3064ATC44-10NAF
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A —
Macrocells 64 —
Usable Gates 1,250 1250
Logic Array Blocks (LABs) 4 (16 macrocells each) —
User I/Os (max) 34 —
Pin-to-Pin Delay (tPD) 10 ns —
Setup Time (tSU) 4.5 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V or 2.5 V —
Packhaging TQFP-44 TQFP-44 (10x10 mm)
Temperature na Operasyon -40C to +85C (Industrial) [DATA_NEEDED: industrial/commercial grade]
Programming Interface JTAG (IEEE Std. 1532 compliant) —
In-System Programmable Yes Yes (IEEE Std. 1532 compliant)
Tindminan RoHS Compliant Compliant
Uri ng Pagpapasok Surface Mount Surface Mount
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Elements / LABs — 4 LABs (16 macrocells per LAB)
Number of I/O Pins — 34
Propagation Delay (tPD, max) — 10 ns
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
I/O Voltage Tolerance — Multi-voltage (3.3 V / 2.5 V / 1.8 V capable)
Programmable Technology — EEPROM (non-volatile)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 JTAG)
Pin-Locking — Yes
Lead Finish — Lead-free (NiPdAu, AF suffix)
Configuration Memory Cycles — 100 erase/program cycles

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