EPM3064ATI44-10NAD vs EPM3064ATC44-10NAF 对比

详细并排对比 EPM3064ATI44-10NAD 出自 Altera 和 EPM3064ATC44-10NAF 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3064ATI44-10NAD EPM3064ATC44-10NAF
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $4.10 $5.05
Family MAX 3000A —
Macrocells 64 —
Usable Gates 1,250 1250
Logic Array Blocks (LABs) 4 (16 macrocells each) —
User I/Os (max) 34 —
Pin-to-Pin Delay (tPD) 10 ns —
Setup Time (tSU) 4.5 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V or 2.5 V —
封装 TQFP-44 TQFP-44 (10x10 mm)
工作温度 -40C to +85C (Industrial) [DATA_NEEDED: industrial/commercial grade]
Programming Interface JTAG (IEEE Std. 1532 compliant) —
In-System Programmable Yes Yes (IEEE Std. 1532 compliant)
RoHS 状态 Compliant Compliant
安装类型 Surface Mount Surface Mount
Series — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Elements / LABs — 4 LABs (16 macrocells per LAB)
Number of I/O Pins — 34
Propagation Delay (tPD, max) — 10 ns
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
I/O Voltage Tolerance — Multi-voltage (3.3 V / 2.5 V / 1.8 V capable)
Programmable Technology — EEPROM (non-volatile)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 JTAG)
Pin-Locking — Yes
Lead Finish — Lead-free (NiPdAu, AF suffix)
Configuration Memory Cycles — 100 erase/program cycles

数据手册与资源

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