EPM3128AFI256-10N vs EPM3256AFC256-7 Comparison
Detailed side-by-side comparison of EPM3128AFI256-10N by Altera and EPM3256AFC256-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3128AFI256-10N | EPM3256AFC256-7 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Logic Density | 2.5K gates | — |
| Macro Cells | 128 | 256 |
| User I/Os | 98 | 161 |
| Speed Grade | -10 (10 ns pin-to-pin) | -7 |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt) | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | IEEE Std. 1532-compliant 3.3-V ISP |
| Package | 256-ball FineLine BGA (FBGA-256) | FBGA-256 (FineLine BGA), 256 balls |
| Operating Temperature | -40C to +85C (industrial, per 'I' suffix) | 0 °C to 70 °C (Commercial) |
| Pin Count | 256 | — |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | EEPROM (non-volatile) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Logic Delay | — | 4.5 ns (max) |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| Core Voltage | — | 3.3 V |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |