EPM3128AFI256-10N vs EPM3256AFC256-7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128AFI256-10N sa pamamagitan ng Altera at EPM3256AFC256-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128AFI256-10N - MAX 3000A CPLD, 128 Macros, 256-FBGA | Altera
EPM3128AFI256-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3128AFI256-10N | EPM3256AFC256-7 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Logic Density | 2.5K gates | — |
| Macro Cells | 128 | 256 |
| User I/Os | 98 | 161 |
| Speed Grade | -10 (10 ns pin-to-pin) | -7 |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Compatibility | 5.0 V, 3.3 V, 2.5 V (MultiVolt) | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | IEEE Std. 1532-compliant 3.3-V ISP |
| Packhaging | 256-ball FineLine BGA (FBGA-256) | FBGA-256 (FineLine BGA), 256 balls |
| Temperature na Operasyon | -40C to +85C (industrial, per 'I' suffix) | 0 °C to 70 °C (Commercial) |
| Bilang ng Pin | 256 | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Configuration Memory | EEPROM (non-volatile) | — |
| PCI Compliance | PCI Local Bus Spec Rev 2.2 | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Logic Delay | — | 4.5 ns (max) |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| Core Voltage | — | 3.3 V |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |