EPM3128AFI256-10N vs EPM3256AFC256-7 对比

详细并排对比 EPM3128AFI256-10N 出自 Altera 和 EPM3256AFC256-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3128AFI256-10N EPM3256AFC256-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $9.75 $12.10
Family MAX 3000A MAX 3000A
Logic Density 2.5K gates —
Macro Cells 128 256
User I/Os 98 161
Speed Grade -10 (10 ns pin-to-pin) -7
Propagation Delay (tPD) 10 ns —
Counter Frequency (max) 227.3 MHz —
Logic Family CMOS, EEPROM-based —
Supply Voltage (Core) 3.3 V —
I/O Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt) 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
In-System Programmability Yes (JTAG / IEEE 1149.1) IEEE Std. 1532-compliant 3.3-V ISP
封装 256-ball FineLine BGA (FBGA-256) FBGA-256 (FineLine BGA), 256 balls
工作温度 -40C to +85C (industrial, per 'I' suffix) 0 °C to 70 °C (Commercial)
引脚数量 256 —
RoHS 状态 Compliant [DATA_NEEDED: RoHS compliance status]
Configuration Memory EEPROM (non-volatile) —
PCI Compliance PCI Local Bus Spec Rev 2.2 —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
Usable Gates — 10,000
Pin-to-Pin Logic Delay — 4.5 ns (max)
Counter Frequency — 227.3 MHz (max)
Propagation Delay (tpd) — 10 ns
Core Voltage — 3.3 V
Process Technology — CMOS EEPROM, 0.30 µm
Boundary-Scan Test — JTAG (IEEE 1149.1)

数据手册与资源

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