EPM3128ATC100-10 vs EPM3064ATC100-10N Comparison
Detailed side-by-side comparison of EPM3128ATC100-10 by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC100-10 - MAX 3000A 128-Macrocell CPLD, 10ns TQFP-100 | Intel / Altera
EPM3128ATC100-10 NrndAltera
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N ✓ ActiveSpecification Comparison
| Parameter | EPM3128ATC100-10 | EPM3064ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Active |
| Device Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 64 |
| User I/Os | 80 | — |
| Usable Gates | 2500 | 1,250 |
| Propagation Delay (tPD) | 10 ns | — |
| Counter Frequency | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| I/O Voltage Tolerance | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Package | 100-pin TQFP | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| In-System Programming | IEEE Std. 1532 compliant (JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (selected speed grades) | — |
| Logic Family | CMOS | — |
| Operating Temperature | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Family | — | MAX 3000A |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| In-System Programmability | — | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |