EPM3128ATC100-10 - MAX 3000A 128-Macrocell CPLD, 10ns TQFP-100 | Intel / Altera
MPN: EPM3128ATC100-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.18 | $11.18 |
| 10 | $10.45 | $104.50 |
| 100 | $9.62 | $962.00 |
| 500 | $8.85 | $4,425.00 |
| 1,000 | $8.1 | $8,100.00 |
Drop-in alternatives for EPM3128ATC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3064ATC100-10
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View Datasheet βEPM3128ATC100-10 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| User I/Os | 80 |
| Usable Gates | 2500 |
| Propagation Delay (tPD) | 10 ns |
| Counter Frequency | 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Voltage Tolerance | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Package | 100-pin TQFP |
| Mounting Type | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) |
| In-System Programming | IEEE Std. 1532 compliant (JTAG) |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (selected speed grades) |
| Logic Family | CMOS |
| Operating Temperature | 0 C to 70 C (commercial) |
EPM3128ATC100-10 Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | I/O β General-purpose user I/O (bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | I/O β General-purpose user I/O (bank 1) |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | VCCINT β 3.3 V core supply |
| Pin 8 | I/O β General-purpose user I/O (bank 2) |
| Pin 9 | I/O β General-purpose user I/O (bank 2) |
| Pin 10 | I/O β General-purpose user I/O (bank 2) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General-purpose user I/O (bank 2) |
| Pin 13 | I/O β General-purpose user I/O (bank 2) |
| Pin 14 | I/O β General-purpose user I/O (bank 2) |
| Pin 15 | I/O β General-purpose user I/O (bank 2) |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β General-purpose user I/O (bank 2) |
| Pin 18 | I/O β General-purpose user I/O (bank 2) |
| Pin 19 | I/O β General-purpose user I/O (bank 2) |
| Pin 20 | I/O β General-purpose user I/O (bank 2) |
| Pin 21 | I/O β General-purpose user I/O (bank 2) |
| Pin 22 | VCCIO2 β I/O bank 2 supply reference |
| Pin 23 | I/O β General-purpose user I/O (bank 2) |
| Pin 24 | I/O β General-purpose user I/O (bank 2) |
| Pin 25 | I/O β General-purpose user I/O (bank 2) |
| Pin 26 | I/O β General-purpose user I/O (bank 2) |
| Pin 27 | I/O β General-purpose user I/O (bank 2) |
| Pin 28 | I/O β General-purpose user I/O (bank 2) |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β General-purpose user I/O (bank 2) |
| Pin 31 | I/O β General-purpose user I/O (bank 2) |
| Pin 32 | I/O β General-purpose user I/O (bank 2) |
| Pin 33 | I/O β General-purpose user I/O (bank 2) |
| Pin 34 | I/O β General-purpose user I/O (bank 2) |
| Pin 35 | I/O β General-purpose user I/O (bank 2) |
| Pin 36 | I/O β General-purpose user I/O (bank 2) |
| Pin 37 | I/O β General-purpose user I/O (bank 2) |
| Pin 38 | GND β Ground |
| Pin 39 | VCCIO2 β I/O bank 2 supply reference |
| Pin 40 | I/O β General-purpose user I/O (bank 2) |
| Pin 41 | I/O β General-purpose user I/O (bank 2) |
| Pin 42 | I/O β General-purpose user I/O (bank 2) |
| Pin 43 | I/O β General-purpose user I/O (bank 2) |
| Pin 44 | I/O β General-purpose user I/O (bank 2) |
| Pin 45 | I/O β General-purpose user I/O (bank 2) |
| Pin 46 | I/O β General-purpose user I/O (bank 2) |
| Pin 47 | I/O β General-purpose user I/O (bank 2) |
| Pin 48 | I/O β General-purpose user I/O (bank 2) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β General-purpose user I/O (bank 3) |
| Pin 51 | I/O β General-purpose user I/O (bank 3) |
| Pin 52 | I/O β General-purpose user I/O (bank 3) |
| Pin 53 | I/O β General-purpose user I/O (bank 3) |
| Pin 54 | I/O β General-purpose user I/O (bank 3) |
| Pin 55 | I/O β General-purpose user I/O (bank 3) |
| Pin 56 | VCCIO3 β I/O bank 3 supply reference |
| Pin 57 | I/O β General-purpose user I/O (bank 3) |
| Pin 58 | I/O β General-purpose user I/O (bank 3) |
| Pin 59 | I/O β General-purpose user I/O (bank 3) |
| Pin 60 | I/O β General-purpose user I/O (bank 3) |
| Pin 61 | I/O β General-purpose user I/O (bank 3) |
| Pin 62 | I/O β General-purpose user I/O (bank 3) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β General-purpose user I/O (bank 3) |
| Pin 65 | I/O β General-purpose user I/O (bank 3) |
| Pin 66 | I/O β General-purpose user I/O (bank 3) |
| Pin 67 | I/O β General-purpose user I/O (bank 3) |
| Pin 68 | I/O β General-purpose user I/O (bank 3) |
| Pin 69 | I/O β General-purpose user I/O (bank 3) |
| Pin 70 | I/O β General-purpose user I/O (bank 3) |
| Pin 71 | I/O β General-purpose user I/O (bank 3) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β General-purpose user I/O (bank 4) |
| Pin 74 | I/O β General-purpose user I/O (bank 4) |
| Pin 75 | I/O β General-purpose user I/O (bank 4) |
| Pin 76 | I/O β General-purpose user I/O (bank 4) |
| Pin 77 | I/O β General-purpose user I/O (bank 4) |
| Pin 78 | I/O β General-purpose user I/O (bank 4) |
| Pin 79 | I/O β General-purpose user I/O (bank 4) |
| Pin 80 | VCCIO4 β I/O bank 4 supply reference |
| Pin 81 | I/O β General-purpose user I/O (bank 4) |
| Pin 82 | I/O β General-purpose user I/O (bank 4) |
| Pin 83 | I/O β General-purpose user I/O (bank 4) |
| Pin 84 | I/O β General-purpose user I/O (bank 4) |
| Pin 85 | I/O β General-purpose user I/O (bank 4) |
| Pin 86 | I/O β General-purpose user I/O (bank 4) |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β General-purpose user I/O (bank 4) |
| Pin 89 | I/O β General-purpose user I/O (bank 4) |
| Pin 90 | I/O β General-purpose user I/O (bank 4) |
| Pin 91 | I/O β General-purpose user I/O (bank 4) |
| Pin 92 | I/O β General-purpose user I/O (bank 4) |
| Pin 93 | I/O β General-purpose user I/O (bank 4) |
| Pin 94 | I/O β General-purpose user I/O (bank 4) |
| Pin 95 | I/O β General-purpose user I/O (bank 4) |
| Pin 96 | GND β Ground |
| Pin 97 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 98 | TMS β JTAG Test Mode Select |
| Pin 99 | TCK β JTAG Test Clock |
| Pin 100 | TDO β JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC100-10 is suitable for 6 applications: PCI Bus Interface Glue Logic, Address Decoding & Chip-Select Generation, Bus-Width & Voltage Translation (5 V to 3.3 V), Glue Logic in Industrial Controllers, Power-Up Sequencing Logic, State Machine Implementation in Test Equipment.
PCI Bus Interface Glue Logic
The EPM3128ATC100-10's PCI-SIG-compliant timing on the -10 speed grade and MultiVolt I/O make it a natural fit for PCI local-bus glue between a 3.3 V controller and 5 V peripherals. With 128 macrocells, the device can decode PCI command/address cycles, generate chip-select strobes, and arbitrate interrupts within a single chip. The 10 ns pin-to-pin delay comfortably meets the PCI 2.2 setup/hold budget at 33 MHz. Engineers typically place the CPLD between the host bridge and downstream peripherals, using the JTAG (IEEE 1532) port for in-field firmware updates.
Recommended
Address Decoding & Chip-Select Generation
In embedded systems with multiple peripherals sharing a parallel bus, the EPM3128ATC100-10's 128 macrocells and 80 I/Os excel at address decoding and chip-select generation. The 10 ns tPD supports fast bus cycles without wait states on most 8/16/32-bit microcontrollers. The device's non-volatile EEPROM configuration means chip-select logic is active at power-on with no boot delay, critical in deterministic-embedded designs. Typical implementations decode 24-bit addresses into 8-16 peripheral selects, freeing the MCU from software-driven decoding.
Recommended
Bus-Width & Voltage Translation (5 V to 3.3 V)
The EPM3128ATC100-10's MultiVolt I/O supports 5.0 V, 3.3 V, and 2.5 V logic levels on the same device while the core runs at 3.3 V, making it an ideal bus-width and voltage translator between legacy 5 V microcontrollers and modern 3.3 V peripherals. With 80 user I/Os the device can bridge full 32-bit data buses plus control signals without external logic. The 10 ns delay is fast enough for parallel bus operation in the low-MHz range commonly used in industrial control boards.
Recommended
Glue Logic in Industrial Controllers
Industrial controllers often require deterministic, instant-on glue logic for sensor multiplexing, encoder decoding, motor-control timing, and power-sequencing tasks. The EPM3128ATC100-10's non-volatile EEPROM, 0-70 C commercial operating range, and 10 ns deterministic delay suit these long-life industrial programs. The 100-pin TQFP package is hand-solderable for low-volume production and reflow-friendly for high-volume assembly. Engineers use the JTAG port for in-field ISP when firmware revisions are needed after deployment.
Recommended
Power-Up Sequencing Logic
Multi-rail systems (FPGA + DDR + analog + MCU) require deterministic power-up sequencing to prevent latch-up and bus contention. The EPM3128ATC100-10's instant-on EEPROM behavior - active at the first clock edge - provides a simple, robust sequencer without boot ROM. With 128 macrocells the device can generate enable strobes for 4-8 power rails with adjustable delay chains implemented in logic. The MultiVolt I/O allows the sequencer to operate at 5 V while monitoring 3.3 V power-good signals.
Recommended
State Machine Implementation in Test Equipment
Bench-top and production test equipment relies on deterministic state machines for handshake protocols, fixture control, and measurement sequencing. The EPM3128ATC100-10 delivers predictable 10 ns state transitions across 128 macrocells, allowing complex multi-state sequencers (UART bridges, SPI/I2C controllers, parallel-test pattern generators) in a single chip. Counter frequencies up to 227.3 MHz support high-speed timing generation. The TQFP-100 footprint is breadboard-friendly with breakout adapters for prototyping.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-7 | EPM3128ATC100-10N | EPM3064ATC100-10 |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Macrocells | 128 | 128 | 128 | 64 |
| User I/Os | 80 | 80 | 80 | 66 |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns | 10 ns | 10 ns |
| Counter Frequency | 227.3 MHz | 227.3 MHz | 227.3 MHz | 222.2 MHz |
| VCCINT | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| I/O Voltage Tolerance | 5.0 V / 3.3 V / 2.5 V | 5.0 V / 3.3 V / 2.5 V | 5.0 V / 3.3 V / 2.5 V | 5.0 V / 3.3 V / 2.5 V |
| Lead-Free / RoHS | [DATA_NEEDED] | [DATA_NEEDED] | Yes (RoHS, lead-free) | [DATA_NEEDED] |
| Unit Price (qty 1, USD) | $11.18 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Higher logic density than 64-macrocell family siblings (vs EPM3064ATC100-10)
- Same-die pin-compatible upgrade path to faster speed grade (vs EPM3128ATC100-7)
- RoHS-compliant lead-free variant available in same package (vs EPM3128ATC100-10N)
Design Notes
The EPM3128ATC100-10 requires a clean 3.3 V VCCINT rail with at least 100 mA of current headroom for I/O switching transients. Decouple each VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, and add a bulk 10 uF tantalum or ceramic capacitor near the package. Each VCCIO bank (1-4) must be tied to the appropriate I/O logic-level supply (5.0 V, 3.3 V, or 2.5 V) and individually bypassed with 0.1 uF capacitors. VCCIO banks may be powered independently, allowing mixed-voltage designs on a single chip.
Route the JTAG signals (TDI, TDO, TMS, TCK) with short, parallel traces and a 10 kohm pull-up on TCK and TMS to prevent spurious boundary-scan activity. Maintain a continuous ground plane under the TQFP-100 package; do not route signal traces beneath the device body. Keep high-speed I/O traces short (< 5 cm) and series-terminate when driving capacitive loads > 25 pF. The exposed thermal pad (if present on TQFP-100) should be soldered to a copper pour to reduce thermal resistance.
Three common pitfalls: (1) Do not leave VCCIO banks floating - unused banks still require their VCCIO pin tied to a valid supply (typically 3.3 V) for the I/O buffers to behave predictably. (2) Do not exceed the 5.0 V I/O absolute-maximum rating even momentarily during hot-plug events; use external clamping if the device may be hot-swapped. (3) Do not assume any speed grade supports all PCI timing - only the -4 to -10 grades are PCI-compliant per the MAX 3000A datasheet; verify PCI bus-timing budgets against the specific speed grade used.
Compliance Information
RoHS / lead-free compliance could not be verified from the verified web data; the -10N variant suffix typically indicates lead-free / RoHS-compliant packaging per Altera naming convention, but this should be confirmed against the manufacturer certificate of compliance (CoC) before use in EU or automotive markets. The part is not AEC-Q100 qualified and is rated for commercial 0 C to 70 C operation only.
