EPM3128ATC100-10NS vs EPM3128ATC100-10N Comparison
Detailed side-by-side comparison of EPM3128ATC100-10NS by Intel and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3128ATC100-10NS
EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel
EPM3128ATC100-10NS ObsoleteAltera
EPM3128ATC100-10N
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndSpecification Comparison
| Parameter | EPM3128ATC100-10NS | EPM3128ATC100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.50 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | β |
| Pin Count | 100 | β |
| Package | TQFP-100 | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Counter Frequency (fCNT) | up to 227.3 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | β |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | β |
| Programmability | In-system (ISP), IEEE Std. 1532 | β |
| Boundary Scan | IEEE 1149.1 JTAG | β |
| Configuration Memory | EEPROM (non-volatile) | CMOS EEPROM (non-volatile, instant-on) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 Β°C to +70 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 2500 |
| Number of I/O | β | 80 |
| Logic Elements / Blocks | β | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Internal Frequency (fMAX) | β | 98 MHz |
| Supply Voltage VCCINT | β | 3.3 V |
| I/O Bank Voltage VCCIO | β | 3.3 V or 2.5 V (selectable) |
| In-System Programming | β | IEEE Std. 1532-compliant ISP via JTAG |
| MSL Level | β | 3 (per JEDEC J-STD-020) |