EPM3128ATC100-10NS vs EPM3128ATC100-10N Comparación
Comparación detallada lado a lado de EPM3128ATC100-10NS por Intel y EPM3128ATC100-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndComparación de especificaciones
| Parámetro | EPM3128ATC100-10NS | EPM3128ATC100-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $6,50 | $5,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | — |
| Recuento de pines | 100 | — |
| Encapsulado | TQFP-100 | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | — |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | — |
| Programmability | In-system (ISP), IEEE Std. 1532 | — |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | CMOS EEPROM (non-volatile, instant-on) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2500 |
| Number of I/O | — | 80 |
| Logic Elements / Blocks | — | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency (fMAX) | — | 98 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Bank Voltage VCCIO | — | 3.3 V or 2.5 V (selectable) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Nivel MSL | — | 3 (per JEDEC J-STD-020) |