EPM3128ATC100-10NS vs EPM3128ATI10010N Comparison
Detailed side-by-side comparison of EPM3128ATC100-10NS by Intel and EPM3128ATI10010N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3128ATC100-10NS | EPM3128ATI10010N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | 80 |
| Pin Count | 100 | — |
| Package | TQFP-100 | 100-pin TQFP |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | — |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | — |
| Programmability | In-system (ISP), IEEE Std. 1532 | — |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Array Blocks (LABs) | — | 8 |
| Usable Gates | — | 2,500 |
| Number of Pins | — | 100 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 98 MHz |
| Core Supply Voltage | — | 3.0 V to 3.6 V |
| I/O Bank Voltage | — | 1.8 V / 2.5 V / 3.3 V |
| Process Technology | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) ISP |
| PCI Compliance | — | Yes (speed grades -5/-6/-7/-10) |