EPM3128ATC100-10NS vs EPM3128ATI10010N 比較
詳細な並列比較: EPM3128ATC100-10NS メーカー: Intel および EPM3128ATI10010N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3128ATC100-10NS | EPM3128ATI10010N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $6.50 | $9.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| User I/Os | 80 | 80 |
| ピン数 | 100 | — |
| パッケージ | TQFP-100 | 100-pin TQFP |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) | — |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V | — |
| Programmability | In-system (ISP), IEEE Std. 1532 | — |
| Boundary Scan | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| 実装タイプ | Surface Mount | Surface Mount |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Array Blocks (LABs) | — | 8 |
| Usable Gates | — | 2,500 |
| ピン数 | — | 100 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 98 MHz |
| Core Supply Voltage | — | 3.0 V to 3.6 V |
| I/O Bank Voltage | — | 1.8 V / 2.5 V / 3.3 V |
| Process Technology | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) ISP |
| PCI Compliance | — | Yes (speed grades -5/-6/-7/-10) |