EPM3128ATC100-5N vs EPM3128ATI100-10 Comparison

Detailed side-by-side comparison of EPM3128ATC100-5N by Intel and EPM3128ATI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-5N EPM3128ATI100-10
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Device Family MAX 3000A —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 128 —
Logic Array Blocks (LABs) 8 (16 macrocells each) —
Usable Gates Up to 10,000 2,500
User I/Os 80 80
Propagation Delay (tPD) 5 ns —
Maximum Internal Frequency 192.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
Programming Technology EEPROM (non-volatile) —
In-System Programmability Yes (IEEE Std. 1532) —
JTAG Boundary Scan Yes (IEEE 1149.1) —
Package TQFP-100 (TC100) TQFP-100 (1.0 mm pitch, 14x14 mm)
Operating Temperature 0 C to +70 C (commercial) -40 °C to +85 °C (industrial)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free]
Family — MAX 3000A
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 128
Logic Elements / LABs — [DATA_NEEDED: LAB count]
Pin-to-Pin Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
MultiVolt I/O Levels — 5.0 V / 3.3 V / 2.5 V compatible
Programmability — EEPROM, 3.3 V in-system (JTAG)
Process Technology — CMOS EEPROM
Open-Drain Output Option — Yes (per I/O pin)
Boundary-Scan (JTAG) — IEEE 1149.1 compliant

Datasheets & Resources

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