EPM3128ATC100-5N vs EPM3128ATI100-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-5N sa pamamagitan ng Intel at EPM3128ATI100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3128ATC100-5N - MAX 3000A CPLD, 128 Macrocells, 80 I/O | Intel
EPM3128ATC100-5N ✓ NakahandaAltera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3128ATC100-5N | EPM3128ATI100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Device Family | MAX 3000A | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| Usable Gates | Up to 10,000 | 2,500 |
| User I/Os | 80 | 80 |
| Propagation Delay (tPD) | 5 ns | — |
| Maximum Internal Frequency | 192.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| Packhaging | TQFP-100 (TC100) | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Temperature na Operasyon | 0 C to +70 C (commercial) | -40 °C to +85 °C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] |
| Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| MultiVolt I/O Levels | — | 5.0 V / 3.3 V / 2.5 V compatible |
| Programmability | — | EEPROM, 3.3 V in-system (JTAG) |
| Process Technology | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Boundary-Scan (JTAG) | — | IEEE 1149.1 compliant |