EPM3128ATC100-5N - MAX 3000A CPLD, 128 Macrocells, 80 I/O | Intel
MPN: EPM3128ATC100-5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.8 | $128.00 |
| 100 | $10.95 | $1,095.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.2 | $8,200.00 |
Drop-in alternatives for EPM3128ATC100-5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM3128ATC100-5N Maximum Ratings & Electrical Characteristics
| Device Family | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) |
| Usable Gates | Up to 10,000 |
| User I/Os | 80 |
| Propagation Delay (tPD) | 5 ns |
| Maximum Internal Frequency | 192.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | Yes (IEEE 1149.1) |
| Package | TQFP-100 (TC100) |
| Operating Temperature | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount |
EPM3128ATC100-5N Pin Configuration
| Pin 1 | I/O — User I/O pin |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | VCCIO — I/O supply voltage (3.3 V or 2.5 V) |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | GND — Ground |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | VCCINT — Core supply voltage (3.3 V) |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | TDI — JTAG Test Data In |
| Pin 46 | TMS — JTAG Test Mode Select |
| Pin 47 | TCK — JTAG Test Clock |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | VCCIO — I/O supply voltage (3.3 V or 2.5 V) |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | VCCINT — Core supply voltage (3.3 V) |
| Pin 82 | GCLK — Global Clock input |
| Pin 83 | OE1 — Output Enable 1 (active low) |
| Pin 84 | OE2/GCLK2 — Output Enable 2 / Global Clock 2 |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | TDO — JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC100-5N is suitable for 7 applications: Address Decoding and Chip-Select Generation, Bus Interface Bridging and Protocol Conversion, Industrial Control and Factory Automation, Telecom Equipment Glue Logic, Embedded System Interrupt Management, Legacy Computer and Peripheral Replacement, Test and Measurement Instrumentation.
Address Decoding and Chip-Select Generation
The EPM3128ATC100-5N is widely deployed in embedded systems for generating chip-select and address-decode signals from a microprocessor bus. With 128 macrocells and 5 ns propagation delay, it can decode complex memory maps including bank-switched Flash, SRAM, and peripheral selects in real time without wait states. The 80 user I/Os accommodate wide address buses (24+ bits) and multiple peripheral select outputs. The deterministic 5 ns tPD ensures the chip-select is valid well within typical MCU access cycles (e.g., 70-100 ns for 8051, ARM7), and the non-volatile EEPROM configuration means the decode logic is available instantly at power-up without bootloader delay. Typical implementation uses the device to consolidate 4-6 discrete 74HC/74FCS decoder ICs into a single CPLD, reducing board area and BOM cost. Quartus II schematic entry with AHDL/VHDL captures the Boolean decode expressions.
Recommended
Bus Interface Bridging and Protocol Conversion
The EPM3128ATC100-5N excels at bridging between legacy and modern bus standards such as PCI-to-ISA, VME-to-PCI, or parallel-FIFO-to-microprocessor bus interfaces. The 5 ns propagation delay is fast enough for 33 MHz PCI bus signal generation including FRAME#, IRDY#, TRDY#, and DEVSEL# timing. With 80 I/Os and 3.3 V/2.5 V VCCIO support, the device can directly interface 3.3 V PCI bus signals and 5.0 V-tolerant inputs allow connection to legacy 5 V peripherals. The EEPROM-based configuration is critical for industrial and telecom systems where instant-on behavior is required without external configuration memory. The device implements bus-master handshaking, address/data multiplexing, and interrupt steering logic in a single chip, replacing dozens of discrete TTL ICs. JTAG boundary scan enables board-level interconnect test.
Recommended
Industrial Control and Factory Automation
The EPM3128ATC100-5N serves as a versatile glue-logic platform in PLC, motor-control, and factory-automation equipment. The 100-pin TQFP package and commercial 0-70 C temperature grade suit factory-floor cabinet environments. The device implements encoder quadrature decoding, PWM generation, stepper-motor pulse-and-direction sequencing, and safety-interlock logic. Its 128 macrocells can hold complete state machines for machine-cycle control, error detection, and emergency-stop sequencing. The JTAG interface (IEEE 1149.1) allows in-system reconfiguration during commissioning or field upgrades without removing the board from the machine. MultiVolt I/O support enables interfacing to 24 V industrial sensors via external opto-couplers and to 3.3 V MCUs. The deterministic timing of CPLDs (vs. MCU firmware loops) makes them ideal for hard-real-time control loops where microsecond-level response is required.
Recommended
Telecom Equipment Glue Logic
In telecom infrastructure such as DSLAMs, optical line terminals, and central-office switches, the EPM3128ATC100-5N provides deterministic glue logic between network processors, ASICs, and physical-layer devices. The 5 ns tPD handles TDM bus timing, Utopia/Serial RapidIO interface glue, and framer/mapper configuration. With 80 I/Os, the device can fan-out control signals from a single network processor to multiple PHYs. The EEPROM configuration ensures the system boots without firmware intervention, critical for carrier-grade equipment requiring deterministic startup. The 3.3 V core with 5 V-tolerant I/O allows interfacing to legacy telecom ASICs while keeping power consumption low. IEEE Std. 1532-compliant ISP enables field updates across thousands of deployed units via JTAG.
Recommended
Embedded System Interrupt Management
The EPM3128ATC100-5N is ideal for priority-encoded interrupt controllers in embedded systems. With 128 macrocells, it can implement a 32-input priority encoder with mask registers, vector generation, and edge/level detection. The 5 ns tPD ensures the interrupt vector is stable within the CPU's interrupt acknowledge cycle. The 80 I/Os allow direct connection to peripheral IRQ outputs (UART, DMA, timers, external interrupts) while presenting a single-vector interface to the host CPU. EEPROM-based configuration means the interrupt map is non-volatile and survives power cycles. The JTAG interface allows live reconfiguration of the interrupt priority map during firmware development, accelerating bring-up. This eliminates the need for discrete 74LS148 priority encoders and 8259A-style interrupt controller ICs.
Recommended
Legacy Computer and Peripheral Replacement
The EPM3128ATC100-5N is widely used to modernize legacy ISA, VLB, and PCI peripheral cards by replacing obsolete discrete logic and TTL ICs. Designs originally using 20-30 discrete 74LS/74F/74ALS ICs for bus arbitration, wait-state generation, and interrupt steering can be consolidated into a single MAX 3000A CPLD. The 5 ns tPD matches legacy 74F-series timing budgets. The 80 I/Os support 16-bit ISA bus implementation with multiple wait-state, DMA, and interrupt signals. Non-volatile EEPROM configuration means the card boots correctly without external boot ROM or configuration memory, simplifying the BOM. The 3.3 V core with 5 V-tolerant I/O allows direct connection to legacy 5 V bus signaling.
Recommended
Test and Measurement Instrumentation
In test equipment such as logic analyzers, protocol analyzers, and ATE (Automated Test Equipment), the EPM3128ATC100-5N provides deterministic timing control for stimulus generation, response capture, and handshake sequencing. The 5 ns tPD enables sub-100 MHz pattern generation with precise edge placement. The 80 I/Os support parallel stimulus/response buses up to 40 channels. MultiVolt I/O allows interfacing with both 3.3 V modern DUTs and 5 V legacy devices. The JTAG boundary scan simplifies board-level test of the instrument itself. The EEPROM configuration allows instant power-up into the last-known test state without firmware boot delay, critical for production-line ATE that must cycle power between tests. The device can implement custom protocols such as I2C, SPI, or UART bridges in test fixtures.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-7N | EPM3128ATC100-10N | EPM3128ATC100-10NS | EPM3128ATC100-10 | EPM3128ATC100-5 |
|---|---|---|---|---|---|---|
| Package | TQFP-100 (TC100) | TQFP-100 (TC100) - same | TQFP-100 (TC100) - same | TQFP-100 (TC100) - same | TQFP-100 (TC100) - same | TQFP-100 (TC100) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 5 ns | 7.5 ns | 10 ns | 10 ns | 10 ns | 5 ns |
| Maximum Internal Frequency | 192.3 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | 192.3 MHz |
| User I/Os | 80 | 80 | 80 | 80 | 80 | 80 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free (RoHS) | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | No (leaded) | No (leaded) |
| In-System Programmable | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) | Yes (IEEE 1532) |
Key Differentiators
- 5 ns propagation delay for high-speed glue logic (vs EPM3128ATC100-7N)
- Lead-free RoHS-compliant packaging (N suffix) (vs EPM3128ATC100-5)
- Non-volatile EEPROM configuration for instant-on behavior (vs SRAM-based FPGAs)
Design Notes
The EPM3128ATC100-5N requires a stable 3.3 V supply for VCCINT (core) and a separate VCCIO rail that can be 3.3 V or 2.5 V. Place a 0.1 uF ceramic decoupling capacitor close to each VCCINT and VCCIO pin, plus a bulk 10-100 uF tantalum or aluminum capacitor near the package. For designs with mixed 3.3 V/2.5 V logic, the VCCIO pins can be split into banks; consult the MAX 3000A datasheet for bank assignments. Inrush current during ISP programming can reach 100-200 mA per VCCINT pin; ensure the regulator has adequate headroom.
The TQFP-100 package has 0.5 mm pitch pins requiring careful PCB layout. Use 0.15 mm/6 mil traces between pads, with ground and power planes on inner layers. Place JTAG connector (TMS, TCK, TDI, TDO) within 50 mm of the CPLD to keep TCK rise times clean. Add 4.7 kohm pull-up resistors on TMS, TDI, and TCK for stable JTAG operation. Keep JTAG traces away from high-speed signal edges to avoid programming glitches. Exposed pad (if present) should be soldered to a grounded copper pour for thermal dissipation.
A common pitfall is assuming the EPM3128ATC100-5N and EPM3128ATC100-5 are interchangeable - the -5N has the 'N' suffix indicating lead-free / RoHS-compliant packaging, while the -5 is leaded. Both share identical pinout and electrical specs but cannot be substituted in RoHS-compliant designs. Another pitfall is overlooking the VCCIO voltage selection: if the VCCIO is set to 2.5 V, the output logic levels are 2.5 V and not 3.3 V, which may cause level-mismatch issues with 3.3 V peripherals. Finally, the device is EEPROM-based with 100+ program/erase cycles; excessive in-system reprogramming can wear out the cells.
Compliance Information
Lead-free per 'N' suffix in MPN. RoHS compliance confirmed by 'N' suffix designation per Altera/Intel packaging convention. Not AEC-Q100 qualified - commercial grade only (0 to +70 C).
