EPM3128ATC144-5N vs EPM3064ATC100-10N Comparison
Detailed side-by-side comparison of EPM3128ATC144-5N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N β ActiveSpecification Comparison
| Parameter | EPM3128ATC144-5N | EPM3064ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $13.75 | $2.43 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS | β |
| Macrocells | 128 | 64 |
| Usable Gates | 2500 | 1,250 |
| User I/O | 96 | β |
| Pin-to-Pin Logic Delay | 5 ns | β |
| Counter Frequency | up to 227.3 MHz | β |
| Supply Voltage (Core) | 3.3 V | β |
| I/O Logic Levels Supported | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | β |
| In-System Programmability | Yes (3.3-V via JTAG) | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| JTAG Boundary Scan | IEEE Std 1149.1 compliant | β |
| Package | 144-pin TQFP (20x20 mm) | 100-pin TQFP |
| Operating Temperature | 0C to 70C (Commercial) | 0C to +70C (commercial) |
| RoHS Status | Compliant (lead-free) | Compliant (lead-free) |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Array Blocks (LABs) | β | 2 |
| Maximum User I/O Pins | β | 66 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 3.3 V (3.0 V to 3.6 V) |
| Boundary-Scan Test (BST) | β | Yes - JTAG compliant |
| Configuration Memory | β | Non-volatile EEPROM |
| Program/Erase Cycles | β | 100 minimum |
| MultiVolt I/O | β | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |