EPM3128ATC144-5N vs EPM3064ATC100-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3128ATC144-5N disebabkan oleh Altera dan EPM3064ATC100-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera
EPM3128ATC144-5N ⚠ Bahagian terakhir untuk beli
Pengandingan Spesifikasi
| Parametr | EPM3128ATC144-5N | EPM3064ATC100-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Aktif |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS | — |
| Macrocells | 128 | 64 |
| Usable Gates | 2500 | 1,250 |
| User I/O | 96 | — |
| Pin-to-Pin Logic Delay | 5 ns | — |
| Counter Frequency | up to 227.3 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Levels Supported | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (3.3-V via JTAG) | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| JTAG Boundary Scan | IEEE Std 1149.1 compliant | — |
| Kemasan | 144-pin TQFP (20x20 mm) | 100-pin TQFP |
| Suhu Operasi | 0C to 70C (Commercial) | 0C to +70C (commercial) |
| Status RoHS | Compliant (lead-free) | Compliant (lead-free) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |