EPM3128ATC144-5N vs EPM3064ATC100-10N 比較
詳細並排比較 EPM3128ATC144-5N 由 Altera 與 EPM3064ATC100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3128ATC144-5N | EPM3064ATC100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Logic Family | CMOS | — |
| Macrocells | 128 | 64 |
| Usable Gates | 2500 | 1,250 |
| User I/O | 96 | — |
| Pin-to-Pin Logic Delay | 5 ns | — |
| Counter Frequency | up to 227.3 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Levels Supported | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (3.3-V via JTAG) | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| JTAG Boundary Scan | IEEE Std 1149.1 compliant | — |
| 封裝 | 144-pin TQFP (20x20 mm) | 100-pin TQFP |
| 工作溫度 | 0C to 70C (Commercial) | 0C to +70C (commercial) |
| RoHS 狀態 | Compliant (lead-free) | Compliant (lead-free) |
| 安裝類型 | Surface Mount | Surface Mount |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |