EPM3128ATI100-10 vs EPM3128ATC100-10N Comparison
Detailed side-by-side comparison of EPM3128ATI100-10 by Altera and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATI100-10
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 β ActiveAltera
EPM3128ATC100-10N
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndSpecification Comparison
| Parameter | EPM3128ATI100-10 | EPM3128ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| User I/Os | 80 | β |
| Logic Elements / LABs | [DATA_NEEDED: LAB count] | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Frequency (fCNT) | up to 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V compatible | β |
| Programmability | EEPROM, 3.3 V in-system (JTAG) | β |
| Package | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial) | 0 Β°C to +70 Β°C (commercial) |
| Process Technology | CMOS EEPROM | β |
| Open-Drain Output Option | Yes (per I/O pin) | β |
| Boundary-Scan (JTAG) | IEEE 1149.1 compliant | β |
| RoHS Status | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] | Compliant |
| Mounting Type | Surface Mount | Surface Mount |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Number of I/O | β | 80 |
| Logic Elements / Blocks | β | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Internal Frequency (fMAX) | β | 98 MHz |
| Supply Voltage VCCINT | β | 3.3 V |
| I/O Bank Voltage VCCIO | β | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | β | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | β | IEEE Std. 1532-compliant ISP via JTAG |
| Lead-Free | β | Yes |
| MSL Level | β | 3 (per JEDEC J-STD-020) |