EPM3128ATI100-10 vs EPM3128ATC100-10N 比較
詳細並排比較 EPM3128ATI100-10 由 Altera 與 EPM3128ATC100-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N Nrnd規格比較
| 參數 | EPM3128ATI100-10 | EPM3128ATC100-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| User I/Os | 80 | — |
| Logic Elements / LABs | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V compatible | — |
| Programmability | EEPROM, 3.3 V in-system (JTAG) | — |
| 封裝 | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| 工作溫度 | -40 °C to +85 °C (industrial) | 0 °C to +70 °C (commercial) |
| Process Technology | CMOS EEPROM | — |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Boundary-Scan (JTAG) | IEEE 1149.1 compliant | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] | Compliant |
| 安裝類型 | Surface Mount | Surface Mount |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Number of I/O | — | 80 |
| Logic Elements / Blocks | — | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency (fMAX) | — | 98 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Bank Voltage VCCIO | — | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | — | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Lead-Free | — | Yes |
| MSL 等級 | — | 3 (per JEDEC J-STD-020) |