EPM3128ATI100-10 vs EPM3128ATC100-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATI100-10 sa pamamagitan ng Altera at EPM3128ATC100-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128ATI100-10 - 128-Macro MAX 3000A CPLD, 10ns TQFP-100 | Altera
EPM3128ATI100-10 ✓ NakahandaAltera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndPagsanggunian na paghahambing
| Parametro | EPM3128ATI100-10 | EPM3128ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| User I/Os | 80 | — |
| Logic Elements / LABs | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | up to 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V compatible | — |
| Programmability | EEPROM, 3.3 V in-system (JTAG) | — |
| Packhaging | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | 0 °C to +70 °C (commercial) |
| Process Technology | CMOS EEPROM | — |
| Open-Drain Output Option | Yes (per I/O pin) | — |
| Boundary-Scan (JTAG) | IEEE 1149.1 compliant | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status -10 suffix historically Pb-free; -10N suffix is lead-free] | Compliant |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Number of I/O | — | 80 |
| Logic Elements / Blocks | — | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency (fMAX) | — | 98 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Bank Voltage VCCIO | — | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | — | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Lead-Free | — | Yes |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |