EPM3256AFC256-10 vs EPM3512AFC256-5C Comparison

Detailed side-by-side comparison of EPM3256AFC256-10 by Altera and EPM3512AFC256-5C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256AFC256-10 EPM3512AFC256-5C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $19.95 $28.95
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 256 β€”
Usable Gates 5,000 10,000
Logic Array Blocks (LABs) 16 (16 macrocells each) β€”
Maximum User I/Os 161 β€”
Propagation Delay (tPD) 10 ns β€”
Internal Counter Frequency (fCNT) 95.2 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Voltage Tolerance 5.0 V tolerant β€”
In-System Programmability Yes (3.3 V ISP via JTAG IEEE 1149.1) β€”
Operating Temperature 0Β°C to +70Β°C (Commercial) 0 Β°C to +70 Β°C (commercial, "C" grade)
Package 256-ball FBGA (Fine-Line BGA) 256-ball FBGA, 17 mm Γ— 17 mm, 1.0 mm pitch
Pitch [DATA_NEEDED: BGA ball pitch] β€”
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Macrocells β€” 512
Maximum Operating Frequency β€” 95.2 MHz
Pin-to-Pin Delay (tPD) β€” 5 ns
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
User I/O Pins β€” 212 (max)
Programming Interface β€” IEEE Std. 1532 / JTAG (4-wire) in-system programmable
Technology β€” EEPROM-based macrocell, non-volatile

Datasheets & Resources

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