EPM3256AFC256-10 vs EPM3512AFC256-5C Comparación
Comparación detallada lado a lado de EPM3256AFC256-10 por Altera y EPM3512AFC256-5C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Última compraAltera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteComparación de especificaciones
| Parámetro | EPM3256AFC256-10 | EPM3512AFC256-5C |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,95 | $28,95 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 (16 macrocells each) | — |
| Maximum User I/Os | 161 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 95.2 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant | — |
| In-System Programmability | Yes (3.3 V ISP via JTAG IEEE 1149.1) | — |
| Temperatura de funcionamiento | 0°C to +70°C (Commercial) | 0 °C to +70 °C (commercial, "C" grade) |
| Encapsulado | 256-ball FBGA (Fine-Line BGA) | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch |
| Pitch | [DATA_NEEDED: BGA ball pitch] | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Macrocells | — | 512 |
| Maximum Operating Frequency | — | 95.2 MHz |
| Pin-to-Pin Delay (tPD) | — | 5 ns |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) |
| User I/O Pins | — | 212 (max) |
| Programming Interface | — | IEEE Std. 1532 / JTAG (4-wire) in-system programmable |
| Technology | — | EEPROM-based macrocell, non-volatile |