EPM3256AFC256-10N vs EPM3128AFI256-10N Comparison
Detailed side-by-side comparison of EPM3256AFC256-10N by Altera and EPM3128AFI256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128AFI256-10N - MAX 3000A CPLD, 128 Macros, 256-FBGA | Altera
EPM3128AFI256-10N β ActiveSpecification Comparison
| Parameter | EPM3256AFC256-10N | EPM3128AFI256-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.95 | $9.75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 5,000 gates | β |
| Macrocells | 256 | β |
| Maximum User I/O | 161 | β |
| Pin-to-Pin Logic Delay | 10 ns | β |
| Maximum Counter Frequency | 227.3 MHz | β |
| Core Voltage | 3.3 V | β |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | β |
| Programmability | EEPROM, in-system programmable (ISP) | β |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | β |
| Package | 256-pin FineLine BGA | 256-ball FineLine BGA (FBGA-256) |
| Logic Family | CMOS | CMOS, EEPROM-based |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | PCI Local Bus Spec Rev 2.2 |
| Operating Temperature | 0 C to 70 C (commercial) | -40C to +85C (industrial, per 'I' suffix) |
| Logic Density | β | 2.5K gates |
| Macro Cells | β | 128 |
| User I/Os | β | 98 |
| Speed Grade | β | -10 (10 ns pin-to-pin) |
| Propagation Delay (tPD) | β | 10 ns |
| Counter Frequency (max) | β | 227.3 MHz |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Compatibility | β | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| In-System Programmability | β | Yes (JTAG / IEEE 1149.1) |
| Pin Count | β | 256 |
| RoHS Status | β | Compliant |
| Configuration Memory | β | EEPROM (non-volatile) |