EPM3256AFC256-10N vs EPM3128AFI256-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-10N sa pamamagitan ng Altera at EPM3128AFI256-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128AFI256-10N - MAX 3000A CPLD, 128 Macros, 256-FBGA | Altera
EPM3128AFI256-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3256AFC256-10N | EPM3128AFI256-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 5,000 gates | — |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Packhaging | 256-pin FineLine BGA | 256-ball FineLine BGA (FBGA-256) |
| Logic Family | CMOS | CMOS, EEPROM-based |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | PCI Local Bus Spec Rev 2.2 |
| Temperature na Operasyon | 0 C to 70 C (commercial) | -40C to +85C (industrial, per 'I' suffix) |
| Logic Density | — | 2.5K gates |
| Macro Cells | — | 128 |
| User I/Os | — | 98 |
| Speed Grade | — | -10 (10 ns pin-to-pin) |
| Propagation Delay (tPD) | — | 10 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| In-System Programmability | — | Yes (JTAG / IEEE 1149.1) |
| Bilang ng Pin | — | 256 |
| Tindminan RoHS | — | Compliant |
| Configuration Memory | — | EEPROM (non-volatile) |