EPM3256AFC256-10N vs EPM3128AFI256-10N 比較
詳細並排比較 EPM3256AFC256-10N 由 Altera 與 EPM3128AFI256-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM3256AFC256-10N | EPM3128AFI256-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 5,000 gates | — |
| Macrocells | 256 | — |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| 封裝 | 256-pin FineLine BGA | 256-ball FineLine BGA (FBGA-256) |
| Logic Family | CMOS | CMOS, EEPROM-based |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | PCI Local Bus Spec Rev 2.2 |
| 工作溫度 | 0 C to 70 C (commercial) | -40C to +85C (industrial, per 'I' suffix) |
| Logic Density | — | 2.5K gates |
| Macro Cells | — | 128 |
| User I/Os | — | 98 |
| Speed Grade | — | -10 (10 ns pin-to-pin) |
| Propagation Delay (tPD) | — | 10 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| In-System Programmability | — | Yes (JTAG / IEEE 1149.1) |
| 腳位數 | — | 256 |
| RoHS 狀態 | — | Compliant |
| Configuration Memory | — | EEPROM (non-volatile) |