EPM3256AFC256-10N vs EPM3512AFC256-18 Comparison
Detailed side-by-side comparison of EPM3256AFC256-10N by Altera and EPM3512AFC256-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteSpecification Comparison
| Parameter | EPM3256AFC256-10N | EPM3512AFC256-18 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $25.95 | $17.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 5,000 gates | β |
| Macrocells | 256 | 512 |
| Maximum User I/O | 161 | β |
| Pin-to-Pin Logic Delay | 10 ns | β |
| Maximum Counter Frequency | 227.3 MHz | β |
| Core Voltage | 3.3 V | β |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | β |
| Programmability | EEPROM, in-system programmable (ISP) | β |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | β |
| Package | 256-pin FineLine BGA | 256-ball FineLine BGA (FCBGA) |
| Logic Family | CMOS | β |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | β |
| Operating Temperature | 0 C to 70 C (commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD1) | β | 18 ns |
| Global Clock Networks | β | 4 |
| VCCINT (Core Supply) | β | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | β | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | β | EEPROM (non-volatile) |
| In-System Programming | β | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | β | 1.0 mm |
| RoHS Status | β | [DATA_NEEDED: not specified in retrieved data] |
| Mounting Type | β | Surface Mount |