EPM3256AFC256-10N vs EPM3512AFC256-18 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3256AFC256-10N disebabkan oleh Altera dan EPM3512AFC256-18 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoletePengandingan Spesifikasi
| Parametr | EPM3256AFC256-10N | EPM3512AFC256-18 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 5,000 gates | — |
| Macrocells | 256 | 512 |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Kemasan | 256-pin FineLine BGA | 256-ball FineLine BGA (FCBGA) |
| Logic Family | CMOS | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| Suhu Operasi | 0 C to 70 C (commercial) | [DATA_NEEDED: industrial/commercial grade] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | — | 1.0 mm |
| Status RoHS | — | [DATA_NEEDED: not specified in retrieved data] |
| Jenis Pemasangan | — | Surface Mount |