EPM3256ATC144-10 vs EPM3256ATC144-10N Comparison
Detailed side-by-side comparison of EPM3256ATC144-10 by Intel and EPM3256ATC144-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 ObsoleteAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N β Last Time BuySpecification Comparison
| Parameter | EPM3256ATC144-10 | EPM3256ATC144-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $14.50 |
| Manufacturer | Intel (formerly Altera) | β |
| Series | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Programmable Type | In-System Programmable (EEPROM-based, IEEE 1532) | β |
| Macrocells | 256 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| Number of I/O Pins | 116 | β |
| Propagation Delay (tpd max) | 10 ns | β |
| Counter Frequency (max) | 95.2 MHz | β |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | β |
| I/O Logic Level Support | MultiVolt - 5.0 V, 3.3 V, 2.5 V | β |
| Operating Temperature | 0 C to +70 C (Commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Package | 144-pin TQFP (20x20 mm) | 144-LQFP (TQFP, ATC suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | β |
| Process Technology | CMOS EEPROM | β |
| RoHS Status | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Macro Cells | β | 256 |
| Number of I/Os | β | 116 |
| Number of Logic Elements / Blocks | β | 16 LABs |
| Supply Voltage (VCCINT) | β | 3.3 V |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| Global Clocks | β | 3 |
| Global Clear / OE | β | Yes (1 global clear, 1 global OE) |
| Program Memory Type | β | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | β | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | β | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | β | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | β | [DATA_NEEDED: not explicitly confirmed in verified data] |