EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
MPN: EPM3256ATC144-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM3256ATC144-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM3256ATC144-10N
β Drop-Inβ In Stock
$14.5 / Unit
View Datasheet βEPM3256ATC144-7
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$17.06 / Unit
View Datasheet βEPM3256ATC144-10AA
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$11.6 / Unit
View Datasheet βEPM3256ATC144-10 Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Series | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device |
| Programmable Type | In-System Programmable (EEPROM-based, IEEE 1532) |
| Macrocells | 256 |
| Logic Array Blocks (LABs) | 16 |
| Usable Gates | 5,000 |
| Number of I/O Pins | 116 |
| Propagation Delay (tpd max) | 10 ns |
| Counter Frequency (max) | 95.2 MHz |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Logic Level Support | MultiVolt - 5.0 V, 3.3 V, 2.5 V |
| Operating Temperature | 0 C to +70 C (Commercial) |
| Package | 144-pin TQFP (20x20 mm) |
| Mounting Type | Surface Mount |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) |
| Process Technology | CMOS EEPROM |
| RoHS Status | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free |
EPM3256ATC144-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | VCCINT β Core 3.3 V supply |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | VCCINT β Core 3.3 V supply |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | I/O β User I/O pin (bank 3) |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | I/O β User I/O pin (bank 3) |
| Pin 51 | VCCINT β Core 3.3 V supply |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | I/O β User I/O pin (bank 4) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 4) |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | VCCINT β Core 3.3 V supply |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 81 | TMS β JTAG Test Mode Select |
| Pin 82 | TCK β JTAG Test Clock |
| Pin 83 | VCCIO4 β I/O bank 4 reference voltage (1.8/2.5/3.3/5.0 V) |
| Pin 84 | I/O β User I/O pin (bank 4) |
| Pin 85 | I/O β User I/O pin (bank 4) |
| Pin 86 | I/O β User I/O pin (bank 4) |
| Pin 87 | VCCINT β Core 3.3 V supply |
| Pin 88 | I/O β User I/O pin (bank 3) |
| Pin 89 | I/O β User I/O pin (bank 3) |
| Pin 90 | I/O β User I/O pin (bank 3) |
| Pin 91 | I/O β User I/O pin (bank 3) |
| Pin 92 | I/O β User I/O pin (bank 3) |
| Pin 93 | GND β Ground |
| Pin 94 | I/O β User I/O pin (bank 3) |
| Pin 95 | I/O β User I/O pin (bank 3) |
| Pin 96 | I/O β User I/O pin (bank 3) |
| Pin 97 | I/O β User I/O pin (bank 3) |
| Pin 98 | I/O β User I/O pin (bank 3) |
| Pin 99 | I/O β User I/O pin (bank 3) |
| Pin 100 | I/O β User I/O pin (bank 3) |
| Pin 101 | I/O β User I/O pin (bank 3) |
| Pin 102 | I/O β User I/O pin (bank 3) |
| Pin 103 | I/O β User I/O pin (bank 3) |
| Pin 104 | VCCINT β Core 3.3 V supply |
| Pin 105 | I/O β User I/O pin (bank 2) |
| Pin 106 | I/O β User I/O pin (bank 2) |
| Pin 107 | I/O β User I/O pin (bank 2) |
| Pin 108 | I/O β User I/O pin (bank 2) |
| Pin 109 | I/O β User I/O pin (bank 2) |
| Pin 110 | GND β Ground |
| Pin 111 | I/O β User I/O pin (bank 2) |
| Pin 112 | I/O β User I/O pin (bank 2) |
| Pin 113 | I/O β User I/O pin (bank 2) |
| Pin 114 | I/O β User I/O pin (bank 2) |
| Pin 115 | I/O β User I/O pin (bank 2) |
| Pin 116 | I/O β User I/O pin (bank 2) |
| Pin 117 | I/O β User I/O pin (bank 2) |
| Pin 118 | I/O β User I/O pin (bank 2) |
| Pin 119 | I/O β User I/O pin (bank 2) |
| Pin 120 | I/O β User I/O pin (bank 2) |
| Pin 121 | VCCINT β Core 3.3 V supply |
| Pin 122 | I/O β User I/O pin (bank 1) |
| Pin 123 | I/O β User I/O pin (bank 1) |
| Pin 124 | I/O β User I/O pin (bank 1) |
| Pin 125 | I/O β User I/O pin (bank 1) |
| Pin 126 | I/O β User I/O pin (bank 1) |
| Pin 127 | GND β Ground |
| Pin 128 | I/O β User I/O pin (bank 1) |
| Pin 129 | I/O β User I/O pin (bank 1) |
| Pin 130 | I/O β User I/O pin (bank 1) |
| Pin 131 | I/O β User I/O pin (bank 1) |
| Pin 132 | I/O β User I/O pin (bank 1) |
| Pin 133 | I/O β User I/O pin (bank 1) |
| Pin 134 | I/O β User I/O pin (bank 1) |
| Pin 135 | I/O β User I/O pin (bank 1) |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 1) |
| Pin 138 | VCCINT β Core 3.3 V supply |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | I/O β User I/O pin (bank 1) |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | TDO β JTAG Test Data Out |
| Pin 143 | GND β Ground |
| Pin 144 | VCCIO1 β I/O bank 1 reference voltage (1.8/2.5/3.3/5.0 V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3256ATC144-10 is suitable for 6 applications: Industrial Bus-Bridge Glue Logic, Address Decoder and Memory Mapping, State-Machine Controller for Embedded Systems, I/O Expansion and GPIO Multiplexer, Telecom Line-Card Glue Logic, Legacy Peripheral Interface Adapter.
Industrial Bus-Bridge Glue Logic
The EPM3256ATC144-10 fits industrial bus-bridge applications because its 256 macrocells provide ample capacity for protocol state machines and address decoding, while the 10 ns tpd guarantees deterministic timing for ISA, PCI, or legacy VME bus cycles. With MultiVolt I/O supporting 5.0 V signaling on legacy industrial buses and 3.3 V on modern MCUs, the same chip bridges mixed-voltage domains without level shifters. The 116 user I/Os comfortably accommodate full 32-bit data plus address and control signals. The IEEE 1532 ISP allows field firmware updates over JTAG for in-service maintenance. Estimated: at 95.2 MHz fMAX the CPLD executes combinatorial decode plus registered handshakes well within the 10 ns budget.
Recommended
Address Decoder and Memory Mapping
For memory-mapping and address-decoding tasks, the EPM3256ATC144-10 delivers 256 macrocells that decode large address spaces (e.g., 24-bit or 32-bit) into multiple chip-select outputs without resorting to cascaded PAL devices. The 10 ns tpd keeps the decoder in-line with synchronous SRAM or NOR flash access times (typically 12-15 ns), so the CPLD adds zero wait states. MultiVolt I/O lets the decoder accept 5.0 V CPU address buses while driving 3.3 V memory devices directly. The EEPROM-based configuration retains mapping at power-up with no boot delay, which is critical for instant-on boot ROM designs.
Recommended
State-Machine Controller for Embedded Systems
The EPM3256ATC144-10 is well suited to embedded state-machine controllers because its LAB-and-macrocell architecture maps cleanly to state diagrams with deterministic 10 ns state transitions regardless of routing. With 16 LABs and 256 macrocells, designers can implement multi-state sequencers for motor control, sensor multiplexing, or industrial protocol stacks (Modbus, CAN glue logic). The 95.2 MHz counter frequency supports timing-sensitive sub-states. JTAG boundary scan simplifies board-level testing of all 116 I/O pins during production, and IEEE 1532 ISP allows firmware revision updates without disassembling the equipment.
Recommended
I/O Expansion and GPIO Multiplexer
The EPM3256ATC144-10 expands MCU GPIO counts by acting as a register-rich I/O extender - 116 user I/Os is sufficient for driving 7-segment displays, keypads, LED matrices, and parallel peripherals simultaneously. The 10 ns tpd keeps I/O updates in sync with the host MCU SPI or parallel bus. MultiVolt I/O allows the MCU to operate at 3.3 V while driving 5.0 V industrial displays. Designers can reconfigure pin assignments via JTAG at any time, making the device ideal for late-stage PCB respins where pinout flexibility saves a board turn.
Recommended
Telecom Line-Card Glue Logic
In telecom line-card applications the EPM3256ATC144-10 implements TDM bus arbitration, clock-domain crossing, and framer glue logic with deterministic timing. The 256 macrocells handle full DS1/E1 or channelized T1 framing alongside HDB3/B8ZS encoding state machines. At 95.2 MHz the device supports clock rates up to 77.76 MHz (STM-1 tributary) when registered logic is used. The 144-TQFP's 116 I/Os accommodate multiple serial framers plus parallel backplane buses. EEPROM retention over 20+ years matches telecom equipment service-life requirements without battery backup.
Recommended
Legacy Peripheral Interface Adapter
The EPM3256ATC144-10 serves as a legacy peripheral interface adapter by emulating discontinued bus controllers (e.g., ISA, VLB, Applebus) in modern FPGA-based systems. Its 116 I/Os support full 16-bit ISA bus emulation plus control signals with margin. The 10 ns tpd matches ISA's 8 MHz bus cycle (125 ns period), and the 256 macrocells implement full DMA arbitration state machines. MultiVolt I/O lets the CPLD interface 5.0 V legacy peripherals from a 3.3 V FPGA host without external level shifters, saving board space and BOM cost.
Recommended
Recommended Products Summary
Engineering reference data for EPM3256ATC144-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3256ATC144-10N | EPM3256ATC144-7 | EPM3256ATC144-10AA |
|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Macrocells | 256 | 256 | 256 | 256 |
| Propagation Delay (tpd max) | 10 ns | 10 ns | 7 ns (faster) | 10 ns |
| Counter Frequency (max) | 95.2 MHz | 95.2 MHz | 125 MHz | 95.2 MHz |
| User I/Os | 116 | 116 | 116 | 116 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| RoHS Compliance | Non-compliant (SnPb) | Compliant (lead-free) | Non-compliant | Non-compliant |
| Lifecycle Status | Obsolete | Obsolete (lead-free) | Obsolete | Obsolete |
Key Differentiators
- Multi-voltage I/O on a 3.3 V core CPLD (vs EPM3128ATC144-10 (lower-density MAX 3000A sibling))
- 256 macrocells vs 128 in the lower-density MAX 3000A parts (vs EPM3128ATC144-10)
- Obsolete legacy part with IEEE 1532 ISP for in-field updates (vs EPM240T100C5N (MAX II active replacement))
Design Notes
The EPM3256ATC144-10 requires a regulated 3.3 V supply on VCCINT (8 pins) and per-bank VCCIO references (5.0 V, 3.3 V, or 2.5 V) on the 4 bank pins. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCCINT pin, plus a single 10 uF bulk tantalum or ceramic capacitor near the package. Estimated: with all 116 I/Os switching at 95 MHz, dynamic core current can reach 150-200 mA, so the regulator must supply at least 300 mA.
The 144-TQFP package dissipates up to ~1 W worst-case under full I/O switching. While no heatsink is required, design the PCB with a copper ground pour directly under the package and stitch vias on the GND pins to inner ground planes. Estimated: theta_JA of the 144-TQFP is approximately 35-40 C/W on a standard 4-layer FR-4 board, yielding a 35-40 C rise at 1 W dissipation.
Route JTAG signals (TDI, TDO, TMS, TCK) as a short daisy-chain with 33 ohm series-termination resistors placed within 25 mm of the CPLD. Keep JTAG traces away from switching I/O banks to avoid noise coupling during ISP programming. Provide a JTAG header footprint (2x5 or 2x10 0.1-inch pitch) accessible from board edge for production programming and boundary-scan test.
Do not leave VCCIO bank pins floating - each bank must be tied to its reference voltage even if some banks are unused. Failing to do so triggers indeterminate I/O behavior and prevents ISP programming. Always read the JTAG IDCODE before issuing program commands to confirm device communication, especially on multi-device JTAG chains where device ordering matters.
Compliance Information
Original EPM3256ATC144-10 is non-RoHS (SnPb finish). Choose the EPM3256ATC144-10N variant for RoHS-compliant lead-free assembly. Per Intel/Altera documentation, both variants are REACH-compliant and conflict-minerals-compliant. Not AEC-Q100 qualified; automotive applications should use MAX II or MAX V families.
