EPM3256ATC144-10 vs EPM3256ATC144-10N Comparação
Comparação detalhada lado a lado de EPM3256ATC144-10 por Intel e EPM3256ATC144-10N por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.
Intel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 ObsoleteAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Última compraComparação de especificações
| Parâmetro | EPM3256ATC144-10 | EPM3256ATC144-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoria | FPGA & CPLD | FPGA & CPLD |
| Status do ciclo de vida | Obsolete | Última compra |
| Status do estoque | In Stock | In Stock |
| Preço unitário (USD) | $9,75 | $14,50 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Programmable Type | In-System Programmable (EEPROM-based, IEEE 1532) | — |
| Macrocells | 256 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| Number of I/O Pins | 116 | — |
| Propagation Delay (tpd max) | 10 ns | — |
| Counter Frequency (max) | 95.2 MHz | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Logic Level Support | MultiVolt - 5.0 V, 3.3 V, 2.5 V | — |
| Temperatura de operação | 0 C to +70 C (Commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Encapsulamento | 144-pin TQFP (20x20 mm) | 144-LQFP (TQFP, ATC suffix) |
| Tipo de montagem | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | — |
| Process Technology | CMOS EEPROM | — |
| Status RoHS | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Macro Cells | — | 256 |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |