EPM3256ATC144-7 vs EPM3256ATI144-7N Comparison

Detailed side-by-side comparison of EPM3256ATC144-7 by Altera and EPM3256ATI144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256ATC144-7 EPM3256ATI144-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $17.06 $10.95
Family MAX 3000A MAX 3000A
Macrocells 256 256
User I/Os 116 β€”
Logic Elements / Gates 600 to 10,000 usable gates β€”
Propagation Delay (tPD) 7.5 ns 7.5 ns (typical)
Counter Frequency (fCNT) 227.3 MHz β€”
Speed Grade -7 β€”
Supply Voltage - Core (VCCINT) 3.3 V β€”
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V β€”
In-System Programming IEEE Std. 1532 compliant, 3.3 V ISP β€”
Package TQFP-144 (LFQFP, gull-wing) TQFP-144 (20 x 20 mm, 0.5 mm pitch)
Operating Temperature 0C to +70C (Commercial) -40C to +85C (industrial)
Pin Count 144 β€”
Mounting Type Surface Mount β€”
PCI Compliance PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) β€”
JTAG Support IEEE Std. 1149.1 boundary-scan β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 5,000
Logic Array Blocks (LABs) β€” 16
Maximum User I/O Pins β€” 116
Maximum Internal Frequency β€” 126.6 MHz
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 2.5 V
MultiVolt I/O Logic Levels β€” 5.0 V / 3.3 V / 2.5 V
Programming Technology β€” EEPROM (in-system programmable)
JTAG / ISP β€” IEEE Std. 1532 compliant
Boundary Scan β€” IEEE Std. 1149.1 (JTAG)
Hot-Socketing Support β€” Yes
RoHS Status β€” Compliant (lead-free)

Datasheets & Resources

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