EPM3256ATC144-7 vs EPM3256ATI144-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256ATC144-7 sa pamamagitan ng Altera at EPM3256ATI144-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256ATC144-7 EPM3256ATI144-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 256 256
User I/Os 116 —
Logic Elements / Gates 600 to 10,000 usable gates —
Propagation Delay (tPD) 7.5 ns 7.5 ns (typical)
Counter Frequency (fCNT) 227.3 MHz —
Speed Grade -7 —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V —
In-System Programming IEEE Std. 1532 compliant, 3.3 V ISP —
Packhaging TQFP-144 (LFQFP, gull-wing) TQFP-144 (20 x 20 mm, 0.5 mm pitch)
Temperature na Operasyon 0C to +70C (Commercial) -40C to +85C (industrial)
Bilang ng Pin 144 —
Uri ng Pagpapasok Surface Mount —
PCI Compliance PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) —
JTAG Support IEEE Std. 1149.1 boundary-scan —
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 5,000
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 116
Maximum Internal Frequency — 126.6 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
MultiVolt I/O Logic Levels — 5.0 V / 3.3 V / 2.5 V
Programming Technology — EEPROM (in-system programmable)
JTAG / ISP — IEEE Std. 1532 compliant
Boundary Scan — IEEE Std. 1149.1 (JTAG)
Hot-Socketing Support — Yes
Tindminan RoHS — Compliant (lead-free)

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