EPM3256ATI144-7N vs EPM3256ATC144-7 Comparison

Detailed side-by-side comparison of EPM3256ATI144-7N by Altera and EPM3256ATC144-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256ATI144-7N EPM3256ATC144-7
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 256 256
Usable Gates 5,000 —
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 116 —
Propagation Delay (tPD) 7.5 ns (typical) 7.5 ns
Maximum Internal Frequency 126.6 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
MultiVolt I/O Logic Levels 5.0 V / 3.3 V / 2.5 V —
Programming Technology EEPROM (in-system programmable) —
JTAG / ISP IEEE Std. 1532 compliant —
Boundary Scan IEEE Std. 1149.1 (JTAG) —
Hot-Socketing Support Yes —
Package TQFP-144 (20 x 20 mm, 0.5 mm pitch) TQFP-144 (LFQFP, gull-wing)
Operating Temperature -40C to +85C (industrial) 0C to +70C (Commercial)
RoHS Status Compliant (lead-free) —
User I/Os — 116
Logic Elements / Gates — 600 to 10,000 usable gates
Counter Frequency (fCNT) — 227.3 MHz
Speed Grade — -7
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 2.5 V / 3.3 V / 5.0 V
In-System Programming — IEEE Std. 1532 compliant, 3.3 V ISP
Pin Count — 144
Mounting Type — Surface Mount
PCI Compliance — PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10)
JTAG Support — IEEE Std. 1149.1 boundary-scan

Datasheets & Resources

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