EPM3256ATI144-7N vs EPM3256ATC144-7 Comparación
Comparación detallada lado a lado de EPM3256ATI144-7N por Altera y EPM3256ATC144-7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteComparación de especificaciones
| Parámetro | EPM3256ATI144-7N | EPM3256ATC144-7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $17,06 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 116 | — |
| Propagation Delay (tPD) | 7.5 ns (typical) | 7.5 ns |
| Maximum Internal Frequency | 126.6 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| MultiVolt I/O Logic Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG / ISP | IEEE Std. 1532 compliant | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) | — |
| Hot-Socketing Support | Yes | — |
| Encapsulado | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | TQFP-144 (LFQFP, gull-wing) |
| Temperatura de funcionamiento | -40C to +85C (industrial) | 0C to +70C (Commercial) |
| Estado RoHS | Compliant (lead-free) | — |
| User I/Os | — | 116 |
| Logic Elements / Gates | — | 600 to 10,000 usable gates |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Speed Grade | — | -7 |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | IEEE Std. 1532 compliant, 3.3 V ISP |
| Recuento de pines | — | 144 |
| Tipo de montaje | — | Surface Mount |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |