EPM3512AFC256-10 vs EPM3512AFC256-21 Comparison

Detailed side-by-side comparison of EPM3512AFC256-10 by Altera and EPM3512AFC256-21 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-10 EPM3512AFC256-21
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $17.50 $18.75
Family MAX 3000A β€”
Macrocells 512 β€”
Logic Array Blocks (LABs) 16 16
Usable Gates 10,000 10,000
Maximum I/O Pins 208 β€”
Pin-to-Pin Delay (tPD) 10 ns β€”
Maximum Counter Frequency 87 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Voltage Tolerance 5-V tolerant β€”
Programmable Technology CMOS EEPROM β€”
In-System Programmability Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) β€”
Package 256-pin FBGA FBGA-256 (FineLine BGA)
Operating Temperature Range [DATA_NEEDED: industrial/commercial operating temperature range] β€”
Pin Count 256 β€”
Mounting Type Surface Mount Surface Mount (BGA)
RoHS Status unknown [DATA_NEEDED: RoHS compliance status]
Architecture MAX (Multiple Array matriX) EEPROM-based β€”
Device Family β€” MAX 3000A
Logic Elements / Macrocells β€” 512 macrocells
Maximum Operating Frequency β€” 87 MHz
Operating Temperature β€” -40C to +85C (industrial)
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (multi-volt I/O)
Programmable Pins (max) β€” [DATA_NEEDED: maximum user I/O pin count]
Programming Interface β€” JTAG / IEEE Std. 1532 ISP
Memory Type β€” Non-volatile EPROM/EEPROM cell array
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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