EPM3512AFC256-10N vs EPM3512AFC256-5C Comparison

Detailed side-by-side comparison of EPM3512AFC256-10N by Altera and EPM3512AFC256-5C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-10N EPM3512AFC256-5C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $43.22 $28.95
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10000 10,000
User I/O Pins 208 212 (max)
Logic Array Blocks (LABs) [DATA_NEEDED: number of LABs] β€”
Operating Frequency (fMAX) [DATA_NEEDED: fMAX MHz] β€”
Pin-to-Pin Delay (tPD) 10 ns 5 ns
Setup Time (tSU) 4.5 ns β€”
VCCINT (Core Supply) 3.3 V β€”
VCCIO (I/O Supply) 3.3 V or 2.5 V β€”
Technology CMOS EEPROM-based, non-volatile EEPROM-based macrocell, non-volatile
Operating Temperature (Commercial) 0 C to +70 C β€”
Package 256-ball FBGA (17 mm x 17 mm) 256-ball FBGA, 17 mm Γ— 17 mm, 1.0 mm pitch
ISP Interface IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Mounting Type Surface Mount (BGA) Surface Mount
MSL Level [DATA_NEEDED: MSL rating] β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type β€” CPLD (Complex Programmable Logic Device)
Maximum Operating Frequency β€” 95.2 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
Operating Temperature β€” 0 Β°C to +70 Β°C (commercial, "C" grade)
Programming Interface β€” IEEE Std. 1532 / JTAG (4-wire) in-system programmable

Datasheets & Resources

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